1. Technical Field
The present disclosure relates to semiconductor device technologies, and in particular, to a semiconductor device having field effect source/drain region(s).
2. Discussion of the Related Art
With higher integration of semiconductor devices, the dimensions of channels in transistors are scaling down. This often exacerbates short channel effects. Short channel effect becomes especially serious as the gate width of transistors approaches several tens of nanometers. In these cases, variation of threshold voltages may result. To overcome the short channel effect, halo junction structures has been proposed. However, this approach reduces on-current and increasing leakage current.
Therefore, the halo junction structure may not be ideal for handling short channel effect in sub-nano scaled flash memory devices.
FIG. 1A is an equivalent circuit diagram of a general semiconductor device, and FIG. 1B is a sectional diagram of a general semiconductor device.
Referring to FIGS. 1A and 1B, a flash memory device includes pluralities of cell strings. Each cell string is constructed of a plurality of memory cell transistors connected between ground and string selection transistors. Each memory cell is comprised of a ground selection line GSL coupled to gate electrodes of the ground selection transistors, and a string selection line SSL coupled to gate electrodes of the string selection transistors. Pluralities of word lines (e.g., WL0-WL31) are arranged between the ground selection lines GSL and the string selection lines SSL. The word lines are coupled with gate electrodes of the memory cell transistors. Source regions of the ground selection transistors link with each other to form a common source line CSL. Drain regions of the string selection transistors are each connected to bit lines BL0-BLn. The bit lines BL0-BLn are each connected to the drain regions of the string selection transistors, crossing over the word lines WL0-WL31.
As shown in FIG. 1B, the word lines WL0-WL31, the ground selection line GSL, and the string selection line SSL are arranged over an active region defined in a semiconductor substrate 10. Cell source/drain regions 12w are formed in the active region between the word lines WL0-WL31. Source/drain regions 12g and 12s are respectively formed in the active region at both sides of the ground selection line GSL and both sides of the string selection line SSL. Between the word lines WL0-WL31 and the substrate 10 are interposed storage regions 14. Each of the storage regions 14 may be comprised of an isolated floating gate, a charge-trapping insulation layer, and/or a nano-crystal conductor in accordance with a kind of cell transistor.
As illustrated in FIG. 1B, the source/drain regions, 12g, 12w, and 12s, of the general semiconductor memory are formed in the structure of PN junctions containing impurities different from those of the substrate 10. Further, the source/drain regions are formed in the junction structure with high breakdown voltage since a high voltage is applied thereto.
As shown in FIG. 2, the general source/drain region is configured in a double-diffused drain (DDD) structure operable in a high breakdown voltage and a small breakdown leakage current. When the semiconductor memory device is, for example, a NAND flash memory device, a writing voltage of 18V is applied to a selected word line during a program operation, the channel and source/drain regions of deselected memory cells coupled to the selected word line are self-boosted up to about 8V. Thus, the source/drain junction structure is designed to be the DDD style equipped with heavily and lightly doped diffusion regions 16 and 18 so as to permit a breakdown voltage of the source/drain junction to be higher than 8V. The DDD junction is useful for reducing leakage current IL, but it may cause a short channel effect, such as punch-through, due to adoption of the lightly-doped diffusion layer and a drain-induced barrier lowering (DIBL) effect due to overlap between the gate electrode (e.g., the word line WL) and the diffusion layer. Such a short channel effect induces extension of sub-threshold leakage and deterioration of sub-threshold swing in the memory cell transistor, further spreading a distribution profile of threshold voltages.